A register that goes through a predetermined sequence of states upon the application of input pulses.
MKL
trigger
toggle
상태전이,state_transition - 상태,state 전이,transition
지연,delay
clock_pulse
state_diagram
trigger
toggle
상태전이,state_transition - 상태,state 전이,transition
지연,delay
clock_pulse
state_diagram
ripple_counter
ripple counter
ripple counter
binary_ripple_counter
binary ripple counter
여러 complemeneting 플립플롭,flip-flop(FF)으로 구성.
각 FF의 출력이 다음 FF의 C input으로 연결.
negative-edge triggered.
BCD_ripple_counter
BCD ripple counter
BCD ripple counter
3-decade BCD counter
3-decade BCD counter
decade :
decade 
decade 
decade#Noun
binary down counter
binary down counter
// ripple counter .... binary ripple counter
여러 complemeneting 플립플롭,flip-flop(FF)으로 구성.
각 FF의 출력이 다음 FF의 C input으로 연결.
negative-edge triggered.
BCD_ripple_counter
BCD ripple counter
BCD ripple counter3-decade BCD counter
3-decade BCD counterdecade :
decade decade decade#Nounbinary down counter
binary down counterripple counter ripple countersynchronous_counter
synchronous counter
// synchronous counter .....synchronous counter synchronous counter
synchronous counter
// synchronous counter .....
synchronous counter synchronous counter
Up: 레지스터,register