베릴로그,Verilog

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IEEE 1364
Ggl:IEEE 1364


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1. 표현

module : module x; .... endmodule
port
instance port
parameter : 값이 compile-time에 결정되는 constant.
net : driven by net drivers.
net driver
"Each bit in a net can take on one of four values: 0, 1, x, or z. In addition, nets can have different driving strengths."
wire - net definition.
reg - register definition.
register
"Registers are storage elements. Values are stored in registers in procedural assignment statements.
Registers can be used as the source for a primitive or module instance (i.e. registers can be connected to input ports), but they cannot be driven in the same way a net can."
4 types of registers: reg / integer / time / real(=realtime)
reg : 항상 unsigned. generic register data type. 1 bit wide to 1 million bits wide.
integer : 32-bit signed. 2의 보수 산술.
time : 64-bit unsigned.
real : 64-bit IEEE floating point.
scalar - 0/1 ... "a single-bit quantity. Both nets and registers may be scalars."
range (in a register definition)
"The range which appears in a register definition
is an indication of how many bits wide the register should be. The form is [msb:lsb], where msb is the most significant bit number, and lsb is the least significant bit number.
The range specifier can used to declare a multi-bit quantity for a register. The Verilog word for a multi-bit quantity is a 'vector'."
vector
bitstring?
memory
1차원 배열,array.
선언 형식은 reg [range] identifier range ;
tri
identifier
instance
primitive instance
module instance
driver
"There may be more than one driver on a net. If there is more than one driver, the value of the net is determined by a resolution function. In Verilog, the possible resolution functions are built-in."
resolution function
driving strength
weak driving strength
strong driving strength
gate
게이트,gate
primitive
predefined module types. Verilog에선 gate라고도 한다. 왜냐면 대개 게이트가 simple logic primitives이기 때문.
1-output
and nand or nor xor xnor
1-input
buf not
tristate - tristate primitive
bufif0 notif0 bufif1 noif1 <- 'notif1'의 오타? - Yes.
"A tristate primitive is one which can produce a 'z' output on a wire."
pull - pull primitive
pullup pulldown
"A pull primitive is one which can drive a 1 or 0 at pull strength on its output. Pull strength is weaker than the default drive strength, so it can be overridden be another primitive driving the same wire with a different value."
build-in primitives
switch
primitive의 class 중 하나. 대개 transistor level에서 모델링에 쓰임.
MOS switches
cmos rcmos nmos rnmos pmos rpmos
bidirectional switches
tran rtran tranif0 rtranif0 tranif1 rtranif1
assignment
blocking / non-blocking
continuous assignment
"sometimes known as data flow statements because they describe how data moves from one place, either a net or register, to another."
LHS는 반드시 net.
simulation
"the execution of a model to reveal its behavior."
... See https://vol.verilog.com/VOL/gmain.htm (Glossary) / Source: https://vol.verilog.com/

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2. Syntax


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2.1. Constant? Integer literal?

비트수를 ' 앞에 배열하는 특이한 문법

ex.
4'b1001 - 4-bit binary number
16'habcd - 16-bit hexadecimal number

logic values
0: logic 0, low, false condition
1: logic 1, high, true condition
z: high impedance value, high-impedance condition of a node or net
x: unknown value, unknown logic value of a node or net


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2.2. Operator


<= non-blocking assignment
= blocking assignment

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3. data type

두 class가 있다
nets: hardware connection points
variables: data storage elements

nets: wire tri wand wor triand trior supply0 supply1 tri0 tri1 trireg
variables: reg integer real time realtime

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4. ko

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5. en

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6. tmp

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6.1. 책 (kpas펌)

Q 베릴로그 문법 등 베릴로그 관련한 책 추천해주실 수 있을까요?
A1
http://staff.ustc.edu.cn/~songch/download/IEEE.1364-2005.pdf - IEEE Standard for Verilog® Hardware Description Language
A2
Verilog HDL : 디지털 설계와 합성의 길잡이 https://g.co/kgs/znKfHb
Verilog를 이용한 디지털 시스템 설계 https://g.co/kgs/k3Dqa7
Verilog HDL을 이용한 디지털 시스템 설계 및 실습 http://kyobo.link/bmQd
2번째 책이 처음 시작하는 사람에게 적당하다고 생각됩니다



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