Difference between r1.10 and the current
@@ -6,15 +6,22 @@
SystemCABEL - [[WpEn:Advanced_Boolean_Expression_Language]]
----
MKL
[[디지털시스템,digital_system]][[디지털_회로,digital_circuit]]
[[디지털회로,digital_circuit]]
[[전자회로,electronic_circuit]][[합성,synthesis]] ... 너무 일반적인 pagename; Ggl:"digital synthesis" or Ggl:"logic synthesis"? pagename TBD
[[게이트,gate]]
[[논리게이트,logic_gate]]
[[논리회로,logic_circuit]]
----
[[WpKo:하드웨어_기술_언어]]
[[WpEn:Hardware_description_language]]
Up: [[언어,language]]; later [[형식_언어,formal_language]]?
Up:
[[언어,language]]; later [[형식언어,formal_language]]?
[[하드웨어,hardware]]
[[기술언어,description_language]]Sub:
베릴로그,Verilog
VHDL (VHSIC Hardware Description Language) - writing
SystemC
ABEL - Advanced_Boolean_Expression_Language
VHDL (VHSIC Hardware Description Language) - writing
SystemC
ABEL - Advanced_Boolean_Expression_Language
MKL
디지털시스템,digital_system
디지털회로,digital_circuit
전자회로,electronic_circuit
합성,synthesis ... 너무 일반적인 pagename; digital synthesis or logic synthesis? pagename TBD
게이트,gate
논리게이트,logic_gate
논리회로,logic_circuit
디지털시스템,digital_system
디지털회로,digital_circuit
전자회로,electronic_circuit
합성,synthesis ... 너무 일반적인 pagename; digital synthesis or logic synthesis? pagename TBD
게이트,gate
논리게이트,logic_gate
논리회로,logic_circuit