하드웨어기술언어,hardware_description_language,HDL

Difference between r1.6 and the current

@@ -1,13 +1,27 @@

#noindex

Sub:
[[베릴로그,Verilog]]

VHDL (VHSIC Hardware Description Language)

SystemVerilog - extension. [[WpEn:SystemVerilog]]

VHDL (VHSIC Hardware Description Language) - writing

SystemC

ABEL - [[WpEn:Advanced_Boolean_Expression_Language]]

----

MKL

[[디지털시스템,digital_system]]

[[디지털_회로,digital_circuit]]

[[디지털회로,digital_circuit]]

[[전자회로,electronic_circuit]]

[[합성,synthesis]] ... 너무 일반적인 pagename; Ggl:"digital synthesis" or Ggl:"logic synthesis"? pagename TBD

[[게이트,gate]]

[[논리게이트,logic_gate]]

[[논리회로,logic_circuit]]

----

~~Up:~~ [[언어~~,language~~]]~~; later~~ [[형식_~~언어,formal~~_language]]

[[WpKo:하드웨어_기술_언어]]

[[WpEn:Hardware_description_language]]

Up:

[[언어,language]]; later [[형식언어,formal_language]]?

[[하드웨어,hardware]]

[[기술언어,description_language]]

Sub:

SystemVerilog - extension.

VHDL (VHSIC Hardware Description Language) - writing
SystemC
ABEL -